/*
 Bug ID: 0012
 Origin: me .
 Version: 0.2b candidate;
 Symptom: deadlock in some unknown circumst.
 Fixing status: fixed in 0.2b. (synchronization primitives rewritten)
*/
module cucu;
wire w;
reg r;

assign w = r;

initial begin
  r = 1;
  #1;
  r = 0;
  #1;
end  
endmodule
